Leadership Role - Formal Verification

Leadership Role - Formal Verification

THE ROLE:

As a member of the UMC Verification team, you will be part of a dedicated organization whose work enables AMD to deliver multiple SoCs to market every year. The UMC is a critical component across Client, Server, Graphics, and Semi-Custom products. We are seeking a Formal Verification Technical Lead with 11+ years of hands-on experience to drive formal verification strategy, execution, and sign-off for complex memory controller designs. In this role, you will define formal scope, lead planning and methodology, prioritize deliverables across multiple blocks, guide the team through convergence and closure, and collaborate effectively with design, architecture, and verification teams across global sites.

This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives.

THE PERSON:

We are looking for a strong formal verification technical leader with deep analytical capability, proven ownership, and the ability to drive a team in a fast-paced, multi-site environment. The ideal candidate will be hands-on in formal methodology, assertions, constraints, proof convergence, and debug, while also providing technical direction, mentoring team members, coordinating priorities, and influencing stakeholders across design, architecture, and verification teams.

KEY RESPONSIBILITIES:

• Work with design team to create FV test plan.
• Build formal verification environment, write assertions, covers and appropriate constraints.
• Create a common formal verification flow so properties and assertions can be ported to different hierarchies.
• Provide Training and mentor new team members.
• Drive formal verification planning, execution, and sign-off across multiple blocks while ensuring quality, schedule adherence, and methodology consistency.
• Lead and mentor the formal verification team, review technical deliverables, resolve execution bottlenecks, and align priorities with global stakeholders across design and verification sites.

PREFERRED EXPERIENCE:

• 16+ years of ASIC/IP verification experience with strong hands-on expertise in formal verification methodology, sign-off, and debug for complex IP or subsystem designs.
• Demonstrated ability to technically lead a formal verification team, manage priorities, provide guidance on methodology, and drive closure in a distributed, multi-site engineering environment.
• Experience with complex CPU/ASIC projects, with demonstrated mastery of successful verification from test planning till tapeout
• Hands on experience in writing SV assertions.
• Exposure to formal methodologies and industry standard Formal tool (like VC Formal, Jasper..).
• Knowledge of scripting using Perl, tcl or equivalent.
• Cache coherency or industry standard AMBA protocol knowledge is a plus

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred
• #LI-SR5

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.