Interconnect Micro-architect/RTL Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation coherent interconnect to provide connectivity between CPU, GPU and special purpose accelerators. Every product that AMD sells has its own custom-designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high-performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!

THE PERSON:

You are an experienced RTL design engineer with strong communication skills. You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and is willing to learn and ready to take on problems. You have a global mindset and ability to work in a multi-site environment are keys to being successful in this role.

KEY RESPONSIBILITIES:

• Early architectural/performance exploration through micro architectural definition and design.
• Optimize the design to meet power, performance, area and timing requirements.
• Write easily readable and synthesizable Verilog RTL.
• Run some unit level testing to deliver quality code to the Design Verification Team.
• Create assertions to improve coverage and cover points to analyze coverage of the design.
• Create well written block level design documentation.
• Participate in post silicon functional and performance debug and tuning.

PREFERRED EXPERIENCE:

• Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
• Excellent knowledge of Verilog and System Verilog
• Working knowledge of C, C++ and a scripting language like Perl or Python
• Strong understanding of digital electronics and high-speed designs(>1GHz).
• Good understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches.
• Good debugging and analytical skills
• Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
• Working knowledge of x86 or ARM ISA is a plus.

ACADEMIC CREDENTIALS:

• Bachelor's, Master's, PhD, or equivalent practical experience in Electrical Engineering, Computer Engineering, or a related technical field preferred.

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.