PD Engineer

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Physical Design Lead Job Summary

We are seeking a highly motivated Physical Design Engineer to join our Silicon Design team. The candidate will be responsible for implementing high-performance ASIC/SoC blocks from synthesis to tapeout while meeting timing, power, area, and reliability targets. The role requires strong expertise in physical design methodologies, EDA tools, and advanced technology nodes.

Key Responsibilities

• Perform physical implementation of digital blocks from netlist to GDSII.
• Execute and optimize:
• Floorplanning
• Power Planning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Physical Verification
• Analyze and close:
• Setup and Hold timing violations
• Signal Integrity issues
• Crosstalk violations
• IR Drop and Electromigration (EM)
• DRC/LVS violations
• Work closely with RTL, Synthesis, DFT, STA, Power, and Verification teams.
• Develop methodologies and automation scripts to improve PD productivity.
• Support tapeout activities and signoff closure.
• Debug physical design issues across advanced technology nodes (5nm/3nm/2nm as applicable).

Required Qualifications

Education

• Bachelor's or Master's degree in:
• Electronics Engineering
• Electrical Engineering
• VLSI Design
• Computer Engineering

Technical Skills

Physical Design Flow

• RTL-to-GDSII implementation
• Floorplanning
• Power Grid Design
• Placement Optimization
• CTS
• Routing
• ECO Implementation
• Timing Closure

Timing Analysis

• Static Timing Analysis (STA)
• OCV/AOCV/POCV concepts
• Multi-mode Multi-corner (MMMC) analysis
• Timing Signoff Closure

Physical Verification

• DRC/LVS
• Antenna Checks
• Density Checks
• LEC awareness

Low Power Design

• UPF/CPF concepts
• Power gating
• Multi-voltage methodologies
• Retention and Isolation strategies

Scripting

Strong scripting skills in:

• Tcl
• Perl
• Python
• Shell scripting

EDA Tools Experience

Experience with one or more:

Synopsys

• ICC2
• Fusion Compiler
• PrimeTime
• StarRC
• IC Validator

Cadence

• Innovus
• Tempus
• Voltus
• Genus

Siemens/Mentor

• Calibre DRC/LVS

Preferred Qualifications

• Experience with advanced technology nodes (16nm/7nm/5nm/3nm).
• Knowledge of high-performance DDR, CPU, GPU, PCIE, AI/ML, Networking, or Data Center SoCs.
• Understanding of package and chiplet integration concepts.
• Experience in hierarchical and full-chip implementation flows.
• Strong debugging and problem-solving skills.
• Excellent communication and collaboration abilities.
• #LI-BM2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.